CPU Caches

Each CPU has it's own cache. Each cache has it's own associated cache controller. Data must be in CPU cache before the work can begin.

Cache memory is organized into lines. Each line of cache can be used to cache a specific location in memory.

A cache may be for

• instructions for the processors, the I-cache
• data, the D-cache
• both instructions and data

Cache Hit

When the CPU makes a reference to the main memory, the cache controller first checks to see if the requested address is in cache. If the requested memory is in cache it is referred as cache-hit.

Cache Miss

When the CPU makes a reference to the main memory, and if the cache controller does not see the requested address in cache, then a cache-miss occurs.

Cache Line Fill

When a cache-miss occurs, the requested memory location must be read from main memory and brought into cache. The process of moving data from RAM to cache is this known as cache line fill.

The processor both reads and writes into cache memory. So when something is written to cache, it must be updated in main memory(RAM) too. The write operation can be configured in two ways

• write-through
• write-back

If write-through caching is enabled, then when a particular line of cache is updated, the corresponding location in memory is updated as well.

If write-back caching is enabled, a write to cache line does not get written back to main memory until the cache line is deallocated.

write-back caching is more efficient than write-through caching.

CPU Cache Types

• Direct Mapped Cache : This is the least expensive type of cache memory. Each line of direct mapped cache can only cache a specific location in memory.
• Fully Associatve Cache Memory : Most flexible type of cache memory and consequently the most expensive one. In fully associative cache, a line can cache any location in main memory.
• Set Associative Cache Memory : Set associative memory provides a good compromise between direct mapped cache and fully associative cache. Most systems use this type of cache. Set associative cache memory is usually referred to as n-way set associative where n is some power of 2. Set associative cache memory allows a memory location to be cached into any one of the n lines of cache.

There can be multiple levels of cache, like L1, L2.

To calculate cache in our system

# x86info -c

Found 2 CPUs

--------------------------------------------------------------------------

CPU #1

Cache info

 L1 Instruction cache: 32KB, 8-way associative. 64 byte line size.

 L1 Data cache: 32KB, 8-way associative. 64 byte line size.

 L2 cache: 1MB, sectored, 8-way associative. 64 byte line size.

--------------------------------------------------------------------------

CPU #2

Cache info

 L1 Instruction cache: 32KB, 8-way associative. 64 byte line size.

 L1 Data cache: 32KB, 8-way associative. 64 byte line size.

 L2 cache: 1MB, sectored, 8-way associative. 64 byte line size.

# getconf -a | grep -i cache

LEVEL1_ICACHE_SIZE                 32768

LEVEL1_ICACHE_ASSOC                8

LEVEL1_ICACHE_LINESIZE             64

LEVEL1_DCACHE_SIZE                 32768

LEVEL1_DCACHE_ASSOC                8

LEVEL1_DCACHE_LINESIZE             64

LEVEL2_CACHE_SIZE                  1048576

LEVEL2_CACHE_ASSOC                 8

LEVEL2_CACHE_LINESIZE              64

LEVEL3_CACHE_SIZE                  0

LEVEL3_CACHE_ASSOC                 0

LEVEL3_CACHE_LINESIZE              0

LEVEL4_CACHE_SIZE                  0

LEVEL4_CACHE_ASSOC                 0

Profiling Cache Usage using valgrind

The following command helps in simulating cache usage

# valgrind --tool=cachegrind <programname>